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Bit
Name
Reset
Access
Description
31:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
4
WRITETRIG
0
W1
Word Write Sequence Trigger
Start write of the first word written to MSC_WDATA, then add 4 to ADDR and write the next word if available within a 30us timeout.
When ADDR is incremented past the page boundary, ADDR is set to the base of the page.
3
WRITEONCE
0
W1
Word Write-Once Trigger
Write the word in MSC_WDATA to ADDR. Flash access is returned to the AHB interface as soon as the write operation completes.
The WREN bit in the MSC_WRITECTRL register must be set in order to use this command.
2
WRITEEND
0
W1
End Write Mode
Write 1 to end write mode when using the WRITETRIG command.
1
ERASEPAGE
0
W1
Erase Page
Erase any user defined page selected by the MSC_ADDRB register. The WREN bit in the MSC_WRITECTRL register must be set
in order to use this command.
0
LADDRIM
0
W1
Load MSC_ADDRB into ADDR
Load the internal write address register ADDR from the MSC_ADDRB register. The internal address register ADDR is incremented
automatically by 4 after each word is written. When ADDR is incremented past the page boundary, ADDR is set to the base of the page.
7.5.5 MSC_ADDRB - Page Erase/Write Address Buffer
Offset
0x010
Reset
Access
Name
Bit Position
Bit
31:0
Name
ADDRB
Reset
0x00000000
Access
RW
Description
Page Erase or Write Address Buffer
This register holds the page address for the erase or write operation. As a page is 512 bytes, bit [8:0] of this register are ignored for
erase commands. For write commands, bit [1:0] are ignored as writes are 32-bit wide only. This register is loaded into the internal
MSC_ADDR register when the LADDRIM field in MSC_CMD is set. The MSC_ADDR register is not readable.
7.5.6 MSC_WDATA - Write Data Register
Offset
0x018
Reset
Access
Name
Bit Position
2011-04-12 - d0001_Rev1.10
34
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